AI System Optimizes Heterogeneous Compute Memory Operations
Summary
USPTO published patent application US20260099366A1 for an AI system that optimizes operations across heterogeneous compute and memory resources, including systems with multiple base dies and attached memory dies. The application discloses methods for identifying and routing operation portions across distributed processing and memory resources.
What changed
USPTO published patent application US20260099366A1 disclosing an AI system that optimizes operations across heterogeneous compute and memory resources. The system identifies first and second portions of operations and routes them to appropriate resources, including configurations with multiple base dies containing processing circuits and attached memory dies. The published application claims methods for dynamically distributing computational workloads across heterogeneous hardware architectures.
Technology companies and manufacturers developing compute systems, memory controllers, or AI accelerators should review the published claims for prior art implications. The application's broad disclosure of heterogeneous compute-memory routing may affect freedom-to-operate assessments for similar optimization techniques.
What to do next
- Monitor USPTO database for related patent publications
- Review the published application for prior art relevance to own products
- Assess freedom-to-operate implications for compute and memory optimization techniques
Archived snapshot
Apr 9, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
SYSTEMS AND METHODS FOR PERFORMING OPERATIONS WITH HETEROGENEOUS COMPUTE AND MEMORY RESOURCES
Application US20260099366A1 Kind: A1 Apr 09, 2026
Inventors
Marie Mai NGUYEN, Rekha PITCHUMANI, Usman SAJID, Yangwook KANG, Yang Seok KI
Abstract
Systems and methods for performing operations with heterogeneous compute and memory resources are disclosed. Data identifying a first portion of an operation and a second portion of the operation may be received. A first set of resources may be caused to perform the first portion of the operation. A second set of resources may be identified based on the operation. The second set of resources may include a first base die including a processing circuit, a memory die attached to the first base die, and a second base die connected to the first base die. The second base die may include a second processing circuit. The second set of resources may be caused to perform the second portion of the operation.
CPC Classifications
G06F 9/5011 G06N 3/0475
Filing Date
2025-07-31
Application No.
19287779
Named provisions
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