Full-Duplex Transceiver With Digital Post-Distortion to Mitigate Self-Interference
Summary
USPTO published patent application US20260100810A1, filed October 8, 2024 (Application No. 18909362), titled 'Full-Duplex Transceiver With Digital Post-Distortion to Mitigate Self-Interference.' The application, filed by inventors Prasidh Ramabadran, Tejinder Dip Singh, Bhargavi Janardhanan, Veeresh Patil, and Bharath Kishore, discloses a transceiver architecture that mitigates self-interference during full-duplex operation using digital post-distortion processing of the received signal.
“A transceiver is provided that mitigates self-interference during full-duplex operation using a digital post-distortion processing of the received signal.”
About this source
USPTO classification H04L covers transmission of digital information: network protocols, modulation schemes, wireless signal processing, coding, encryption in transit, and multiplexing. With 5G, 6G, and satellite internet driving new filings, H04L is one of the largest active patent classes. Every newly published application in H04L lands in this feed, around 215 a month. Applications publish 18 months after filing, so this feed reveals what MediaTek, Qualcomm, Ericsson, Samsung, Huawei, and dozens of smaller companies were working on in the prior year and a half. Watch this if you compete in networking hardware, advise telecoms on IP strategy, or scout acquisition targets in wireless infrastructure.
What changed
USPTO published patent application US20260100810A1, disclosing a full-duplex transceiver design that uses digital post-distortion processing to cancel self-interference caused by the transmit chain. The application covers CPC classifications H04L 5/1423, H04B 1/0096, H04L 25/03006, and H04L 2025/03433, indicating relevance to communication systems and signal processing.
Technology manufacturers developing full-duplex wireless communication devices should review the application's claims to assess potential patent landscape implications for their own R&D and product development activities. The digital post-distortion technique disclosed represents a technical approach to interference mitigation that may be relevant to next-generation communication system design.
Archived snapshot
Apr 22, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
FULL-DUPLEX TRANSCEIVER WITH DIGITAL POST-DISTORTION TO MITIGATE SELF-INTERFERENCE CAUSED BY TRANSMIT CHAINS
Application US20260100810A1 Kind: A1 Apr 09, 2026
Inventors
Prasidh RAMABADRAN, Tejinder Dip SINGH, Bhargavi JANARDHANAN, Veeresh PATIL, Bharath KISHORE
Abstract
A transceiver is provided that mitigates self-interference during full-duplex operation using a digital post-distortion processing of the received signal.
CPC Classifications
H04L 5/1423 H04B 1/0096 H04L 25/03006 H04L 2025/03433
Filing Date
2024-10-08
Application No.
18909362
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