USPTO Patent Grant: Synopsys Connectivity Controller
Summary
The USPTO has granted patent US12587311B1 to Synopsys, Inc. for a connectivity controller with enhanced throughput in an embedded system. The patent, filed on May 21, 2024, details a system designed to improve packet handling and integrity checks in computing devices.
What changed
The United States Patent and Trademark Office (USPTO) has issued patent US12587311B1 to Synopsys, Inc. This patent covers a connectivity controller designed for embedded systems, focusing on enhancing throughput. Key features include a host controller and a device controller that communicate according to a connectivity standard, with specific mechanisms to inhibit integrity checks and utilize pre-computed CRC values under certain conditions, thereby optimizing packet processing.
This patent grant is primarily an intellectual property matter and does not impose new regulatory obligations on businesses. However, companies involved in developing or utilizing embedded systems, particularly those related to networking and data communication, may find the patented technology relevant to their product development or licensing strategies. The filing date was May 21, 2024, and the patent is set to grant on March 24, 2026.
Archived snapshot
Mar 27, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
Connectivity controller with enhanced throughput in an embedded system
Grant US12587311B1 Kind: B1 Mar 24, 2026
Assignee
Synopsys, Inc.
Inventors
Saleem Chisty Mohammad
Abstract
A computing system includes, in part, a host controller and a device controller. The host controller is configured to comply with a connectivity standard and includes, in part, a host protocol layer, a host link layer, and a host register. The device controller is configured to communicate with the host controller in conformity with the connectivity standard. The device controller includes, in part, a device protocol layer, a device link layer, and a device register. In response to the device register being set, the device link layer is inhibited from performing an integrity check on a packet received from the host link layer and using a first cyclic redundancy check (CRC) value of the first packet. The CRC value is computed by and disposed in the first packet by the host link layer.
CPC Classifications
H03M 13/09 G06F 9/5005 G06F 9/30079 G06F 11/1004 G06T 1/20 H04L 1/0061
Filing Date
2024-05-21
Application No.
18670307
Claims
20
Named provisions
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