Semiconductor Switch Reduces Data Exchange Latency
Summary
NXCoreBase Semiconductor Corporation has filed patent application US20260113279A1 for a multi-port switch architecture and data transmission method intended to reduce data exchange latency. The switch uses dedicated buffers at each port's receiving and sending ends, with a request-acknowledgment handshake that enables the receiving end to forward data to other ports' sending ends as soon as a destination address match is confirmed. By overlapping reception and forwarding operations, the disclosed system can reduce data exchange latency and improve data transmission efficiency in semiconductor-based switching applications.
“The present disclosure can reduce data exchange latency and improve data transmission efficiency.”
About this source
USPTO classification H04L covers transmission of digital information: network protocols, modulation schemes, wireless signal processing, coding, encryption in transit, and multiplexing. With 5G, 6G, and satellite internet driving new filings, H04L is one of the largest active patent classes. Every newly published application in H04L lands in this feed, around 215 a month. Applications publish 18 months after filing, so this feed reveals what MediaTek, Qualcomm, Ericsson, Samsung, Huawei, and dozens of smaller companies were working on in the prior year and a half. Watch this if you compete in networking hardware, advise telecoms on IP strategy, or scout acquisition targets in wireless infrastructure.
What changed
NXCoreBase Semiconductor Corporation filed patent application US20260113279A1 with the USPTO on October 15, 2025, covering a switch, data transmission method, and system for reducing data exchange latency. The invention uses a multi-port switch architecture where each port's receiving end buffers incoming data containing a destination address and immediately sends a request to other ports' sending ends. Upon acknowledgement from the matching port, data is forwarded in parallel, reducing idle waiting time. CPC classifications H04L 47/28 and H04L 47/30 indicate relevance to congestion control and data flow optimisation in telecommunications networks.
Companies operating in semiconductor switching, networking equipment manufacturing, and data centre infrastructure design should monitor this application to assess whether the disclosed buffer-and-acknowledgement technique resembles approaches they use or have under development. Inventors Hong-Chain Chen and Chia-Chi Chen assigned the application to NXCoreBase Semiconductor Corporation, with the filing entering the public record upon April 23, 2026 publication.
Archived snapshot
Apr 24, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
SWITCH, DATA TRANSMISSION METHOD, AND SYSTEM FOR REDUCING DATA EXCHANGE LATENCY
Application US20260113279A1 Kind: A1 Apr 23, 2026
Assignee
NXCoreBase Semiconductor Corporation
Inventors
Hong-Chain Chen, Chia-Chi Chen
Abstract
The present disclosure discloses a switch, a data transmission method, and a system for reducing data exchange latency. The switch comprises a plurality of data transmission ports electrically interconnected. Each port comprises a receiving end and a sending end, and the receiving end and the sending end are respectively configured with a buffer. The receiving end receives and forwards the data to the sending ends of other ports. The receiving end receives and stores data comprising a destination address into corresponding buffer. When completing reception of the destination address, the receiving end sends a request including the destination address to the sending ends. The sending end whose port address matches the destination address returns an acknowledgement to the receiving end. Upon receiving the acknowledgement, the receiving end sends data to the corresponding sending end. The present disclosure can reduce data exchange latency and improve data transmission efficiency.
CPC Classifications
H04L 47/28 H04L 47/30
Filing Date
2025-10-15
Application No.
19359124
Mentioned entities
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