Layer-wise Precision Optimization in Analog Compute-in-Memory Accelerators

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LAYER-WISE PRECISION OPTIMIZATION IN ANALOG COMPUTE-IN-MEMORY ACCELERATORS

Application US20260093972A1 Kind: A1 Apr 02, 2026

Assignee

Intel Corporation

Inventors

Shamik Kundu, Arnab Raha, Richard Dorrance, Deepak Abraham Mathaikutty, Brent Carlton

Abstract

It is not optimal to apply analog compute-in-memory circuitry (ACiM) for all layers of a neural network or to apply digital compute-in-memory (DCiM) circuitry for all layers of the neural network, due to the tradeoff between efficiency and precision. To address this challenge, a layer-wise offloading strategy can selectively execute neural network layers using either DCiM circuitry or ACIM circuitry based on signal and statistical sensitivity conditions. The approach leverages a combined heuristic, incorporating both the number of input channels meeting a signal sensitivity criterion and the statistical properties of the weight distribution meeting a statistical sensitivity criterion. Layers are allocated to DCiM when both conditions are satisfied, while layers are allocated to ACIM if either or both conditions are not met. The approach optimizes computational efficiency by dynamically assigning resources according to input characteristics and distributional metrics.

CPC Classifications

G06N 3/065 G06F 15/7821

Filing Date

2025-12-09

Application No.

19413190

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