Variable-bit Adaptive Sensing Circuit for Analog Neuromorphic Systems
Summary
USPTO published patent application US20260099703A1 for a variable-bit adaptive sensing circuit system designed for analog neuromorphic systems. The system comprises a sensing circuit, error detection circuit, and analog-to-digital conversion circuit for processing synapse array outputs. The application was filed on April 22, 2025, and names Hyung Min Lee, Min Seong Um, and Min Il Kang as inventors.
What changed
USPTO published patent application US20260099703A1, a technical disclosure for a variable-bit adaptive sensing circuit system in analog neuromorphic systems. The system includes a sensing part circuit to detect output currents from synapse devices in synapse array columns, an error detection circuit to identify errors and establish operation start references, and an analog-to-digital conversion circuit to integrate and convert synapse device currents into digital values.
Technology companies and semiconductor manufacturers developing neuromorphic computing systems should monitor this application for potential future patent claims that may affect product development. While patent applications do not create immediate compliance obligations, granted patents from this application could impact freedom-to-operate analyses for neuromorphic chip designers.
Archived snapshot
Apr 17, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
VARIABLE-BIT ADAPTIVE SENSING CIRCUIT SYSTEM IN ANALOG NEUROMORPHIC SYSTEMS
Application US20260099703A1 Kind: A1 Apr 09, 2026
Inventors
Hyung Min LEE, Min Seong UM, Min Il KANG
Abstract
A variable-bit adaptive sensing circuit system in an analog neuromorphic system is disclosed. In an analog neuromorphic system including a synapse array, the circuit system for sensing the synapse array comprises: a sensing part circuit configured to sense output currents of synapse devices in each column of the synapse array in response to an operation signal; an error detection circuit configured to detect errors based on the column-wise output currents of the synapse devices and determine an operation start reference; and an analog-to-digital conversion circuit configured to integrate the synapse device current based on the operation start reference, convert the integrated current into a voltage value, and output a corresponding digital value.
CPC Classifications
G06N 3/065 G01R 31/3163
Filing Date
2025-04-22
Application No.
19185582
Related changes
Get daily alerts for USPTO Patent Applications - AI & Computing (G06N)
Daily digest delivered to your inbox.
Free. Unsubscribe anytime.
Source
About this page
Every important government, regulator, and court update from around the world. One place. Real-time. Free. Our mission
Source document text, dates, docket IDs, and authority are extracted directly from USPTO.
The summary, classification, recommended actions, deadlines, and penalty information are AI-generated from the original text and may contain errors. Always verify against the source document.
Classification
Who this affects
Taxonomy
Browse Categories
Get alerts for this source
We'll email you when USPTO Patent Applications - AI & Computing (G06N) publishes new changes.
Subscribed!
Optional. Filters your digest to exactly the updates that matter to you.