Accelerating neural networks in hardware using interconnected crossbars
Summary
The USPTO granted Patent US12596922B2 to Google LLC on April 7, 2026, covering a computing unit design for accelerating neural networks using interconnected analog crossbar circuits. The patent includes 20 claims relating to matrix weight operations performed on analog signals within crossbar architectures. Inventors are Pierre-Luc Cantin and Olivier Temam, with filing date March 21, 2024.
What changed
The USPTO has granted a new patent to Google LLC covering hardware acceleration of neural networks using interconnected analog crossbar circuits. The invention includes digital-to-analog and analog-to-digital conversion units integrated with multiple analog crossbar circuits that perform matrix weight operations on analog signals.
Technology companies developing AI accelerators, neural network hardware, or crossbar-based computing systems should consider this patent when assessing intellectual property landscape and potential licensing obligations for similar architectures.
What to do next
- Monitor for potential licensing requirements if developing similar neural network acceleration hardware
- Review patent claims for freedom-to-operate analysis in AI hardware development
Archived snapshot
Apr 7, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
Accelerating neural networks in hardware using interconnected crossbars
Grant US12596922B2 Kind: B2 Apr 07, 2026
Assignee
Google LLC
Inventors
Pierre-Luc Cantin, Olivier Temam
Abstract
A computing unit for accelerating a neural network is disclosed. The computing unit include an input unit that includes a digital-to-analog conversion unit and an analog-to-digital conversion unit that is configured to receive an analog signal from the output of a last interconnected analog crossbar circuit of a plurality of analog crossbar circuits and convert the second analog signal into a digital output vector, and a plurality of interconnected analog crossbar circuits that include the first interconnected analog crossbar circuit and the last interconnected crossbar circuits, wherein a second interconnected analog crossbar circuit of the plurality of interconnected analog crossbar circuits is configured to receive a third analog signal from another interconnected analog crossbar circuit of the plurality of interconnected crossbar circuits and perform one or more operations on the third analog signal based on the matrix weights stored by the crosspoints of the second interconnected analog crossbar.
CPC Classifications
G06N 3/065 G06N 3/04 G06N 3/08 G06F 9/5027 G06F 17/16
Filing Date
2024-03-21
Application No.
18612881
Claims
20
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