Google LLC Patent for Distributed Computing Pipeline Processing

ChangeBridge: Patent Grants - AI & Computing (G06N)

Published March 24th, 2026

Detected March 24th, 2026

Summary

The USPTO has granted Google LLC a patent (US12585495B2) for a distributed computing pipeline processing system. The patent covers methods for processing computational graphs on distributed devices, including assigning operations to computing devices and hardware accelerators for parallel execution.

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What changed

The United States Patent and Trademark Office (USPTO) has granted Google LLC patent US12585495B2 for a novel method of distributed computing pipeline processing. The patent details a system designed to process computational graphs across multiple distributed computing devices and hardware accelerators. Key aspects include the parallel assignment of initial operations to computing devices and subsequent operations to interconnected hardware accelerators, which receive inputs from queues managed by the computing devices.

This patent grant signifies a new intellectual property for Google in the area of advanced computing infrastructure. While not a regulatory rule, it represents innovation in distributed systems that could influence future technology development and adoption. Compliance officers in the technology sector, particularly those involved with AI and cloud computing infrastructure, should be aware of this patent as it may impact competitive landscapes and technology roadmaps.

Source document (simplified)

← USPTO Patent Grants

Distributed computing pipeline processing

Grant US12585495B2 Kind: B2 Mar 24, 2026

Assignee

Google LLC

Inventors

Rohan Anil, Battulga Bayarsaikhan, Ryan P. Doherty, Emanuel Taropa

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing computational graphs on distributed computing devices. One of the methods includes receiving a request to execute a processing pipeline (i) first operations that transform raw inputs into pre-processed inputs and (ii) second operations that operate on the pre-processed inputs; and in response: assigning the first operations to two or more of a plurality of computing devices, assigning the second operations to one or more hardware accelerators of a plurality of hardware accelerators, wherein each hardware accelerator is interconnected with the plurality of computing devices, and configured to (i) receive inputs from respective queues of the two or more computing devices assigned the first operations and (ii) perform the second operations on the received pre-processed inputs, and executing, in parallel, the processing pipeline on the two or more computing devices and the one or more hardware accelerators.