Systolic Parallel Galois Hash Computing Device Patent Grant

ChangeBridge: Patent Grants - Networking (H04L)

Published April 7th, 2026

Detected April 7th, 2026

Summary

USPTO granted Patent US12596530B2 to Secturion Systems, Inc. for a systolic parallel Galois hash computing device. The invention comprises multiple circuits processing data packets using multipliers and exclusive-OR gates to compute Galois hashes, applicable in FPGA and integrated circuit implementations. The patent includes 19 claims covering the hardware architecture for cryptographic hash operations in networking applications.

View original document View source feed page

What changed

USPTO issued Patent US12596530B2 titled 'Systolic parallel galois hash computing device' to Secturion Systems, Inc. The patent covers a computing device with multiple circuits that process incoming packet data through first and second multipliers and exclusive-OR gates to compute Galois hashes. The device architecture enables parallel processing suitable for FPGA and integrated circuit implementations.

For manufacturers of cryptographic hardware, FPGAs, and integrated circuits, this patent establishes intellectual property protection for systolic parallel Galois hash computation methods. Companies developing network security equipment, data validation systems, or packet processing hardware should review this patent to ensure their products do not infringe on the protected circuit configurations and XOR-based multiplier arrangements described in the 19 claims.

What to do next

Monitor for updates

Source document (simplified)

← USPTO Patent Grants

Systolic parallel galois hash computing device

Grant US12596530B2 Kind: B2 Apr 07, 2026

Assignee

SECTURION SYSTEMS, INC.

Inventors

Sean Little, Jordan Anderson

Abstract

A computing device (e.g., an FPGA or integrated circuit) processes an incoming packet comprising data to compute a Galois hash. The computing device includes a plurality of circuits, each circuit providing a respective result used to determine the Galois hash, and each circuit including: a first multiplier configured to receive a portion of the data; a first exclusive-OR gate configured to receive an output of the first multiplier as a first input, and to provide the respective result; and a second multiplier configured to receive an output of the first exclusive-OR gate, wherein the first exclusive-OR gate is further configured to receive an output of the second multiplier as a second input. In one embodiment, the computing device further comprises a second exclusive-OR gate configured to output the Galois hash, wherein each respective result is provided as an input to the second exclusive-OR gate.