FPGA Data Transfer Over Packet-Based Network-on-Chip

ChangeBridge: Patent Apps - Networking (H04L)

Detected March 26th, 2026

Summary

The USPTO has published a new patent application, US20260089124A1, detailing a method for FPGA data transfer over a packet-based network-on-chip. The application, filed on September 25, 2024, describes techniques for efficient data transmission within integrated circuit devices.

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What changed

This document is a publication of a new patent application (US20260089124A1) by the USPTO, filed on September 25, 2024. The application describes an invention related to data transfer over a packet-based network-on-chip (NoC) within integrated circuit devices, focusing on Field-Programmable Gate Arrays (FPGAs). It details how programmable logic regions can act as interface circuits to receive, concatenate, and transmit data packets, and unpack them at a destination.

As this is a patent application publication, there are no immediate compliance obligations or deadlines for regulated entities. However, companies involved in semiconductor design, integrated circuit manufacturing, or network-on-chip technologies may find the described technical innovations relevant to their research and development efforts. It signifies a new area of intellectual property protection in this technological domain.

Source document (simplified)

← USPTO Patent Applications

FPGA DATA TRANSFER OVER NETWORK-ON-CHIP (NOC)

Application US20260089124A1 Kind: A1 Mar 26, 2026

Inventors

Hossein OMIDIAN SAVARBAGHI, Dinesh D. GAITONDE

Abstract

Data transfer over a packet-based network-on-chip (NoC) of an integrated circuit device, including an example in which a first region of programmable logic (PL) serves as a first interface circuit between a first circuit block and a NoC master unit (NMU), to receive first and second data via respective first and second channels of the first circuit block based on a communication protocol of the first circuit block, concatenate the first and second data to provide the concatenated content, and transmit the concatenated content to the NMU. The NoC may route the packets from the NMU to a NoC slave unit (NSU) associated with a second circuit block via a pre-determined route of the NoC that is dedicated to traffic between the first and second circuit blocks. A second region of the PL serves as an interface circuit between the NSU and the second block to unpack the data.