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Integration Structure for Connecting Semiconductor Devices

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Published March 25th, 2026
Detected April 1st, 2026
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Summary

The European Patent Office published European patent EP4188061A1, filed by Commissariat à l'Energie Atomique et aux Energies Alternatives, covering an integration structure for connecting semiconductor devices, including associated methods, assembly and system configurations. The patent encompasses H10N, H10W, and G06N classification codes including quantum computing applications (G06N10/40). Designated validation states include all major European economies (DE, FR, GB, IT, ES, NL, BE, CH, AT, SE, PL).

What changed

EPO published patent EP4188061A1 granting Commissariat à l'Energie Atomique et aux Energies Alternatives exclusive rights to an integration structure for connecting semiconductor devices, including methods, assembly and system configurations. The invention is classified under H10N 60/01, H10N 69/00, H10W 70 series, and G06N 10/40 (quantum computing), indicating applicability to advanced semiconductor and quantum computing technologies. The patent is validated across 37 designated European states.

Patent publications do not impose compliance obligations but grant exclusive intellectual property rights. Companies developing similar semiconductor integration technologies or operating in quantum computing should review the patent claims to ensure their activities do not infringe on the protected integration structures and methods. No specific compliance deadlines or penalties are associated with this patent grant.

Source document (simplified)

← EPO Patent Bulletin

INTEGRATION STRUCTURE FOR CONNECTING A PLURALITY OF SEMICONDUCTOR DEVICES, METHODS, ASSEMBLY AND SYSTEM THEREOF

Publication EP4188061A1 Kind: A1 Mar 25, 2026

Applicants

Commissariat à l'Energie Atomique et aux Energies
Alternatives

Inventors

CHARBONNIER, Jean, DESCHASEAUX, Edouard, THOMAS, Candice

IPC Classifications

H10N 60/01 20230101AFI20260218BHEP H10N 69/00 20230101ALI20260218BHEP H10W 70/63 20260101ALI20260218BHEP H10W 70/65 20260101ALI20260218BHEP H10W 70/66 20260101ALI20260218BHEP H10W 70/698 20260101ALI20260218BHEP G06N 10/40 20220101ALI20260218BHEP

Designated States

AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, ME, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR

View original document →

Named provisions

Integration Structure for Connecting Semiconductor Devices Methods for Semiconductor Device Integration Assembly and System Configurations

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Classification

Agency
EPO
Published
March 25th, 2026
Instrument
Notice
Legal weight
Non-binding
Stage
Final
Change scope
Minor
Document ID
EP4188061A1

Who this affects

Applies to
Technology companies Manufacturers
Industry sector
3341 Computer & Electronics Manufacturing
Activity scope
Patent Protection Semiconductor Device Integration Quantum Computing Technology
Geographic scope
European Union EU

Taxonomy

Primary area
Intellectual Property
Operational domain
Legal, Research and Development
Topics
Semiconductor Manufacturing Technology Electronics

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