Efficient Bit Sequence Transmission, Restricted Disparity, Error Correction
Summary
INOVA SEMICONDUCTORS GMBH filed patent application US20260113145A1 on April 23, 2026, covering a method for generating bit sequences with limited disparity and run length enabling efficient data transmission on transmission channels with deterministic physical behavior control. The invention uses encoders designed with minimal gates and incorporates nesting for efficient correction of burst errors. The application was originally filed on December 18, 2025 as Application No. 19425573.
“The proposed method allows data to be able to be transmitted particularly efficiently on a transmission channel.”
About this source
USPTO classification H04L covers transmission of digital information: network protocols, modulation schemes, wireless signal processing, coding, encryption in transit, and multiplexing. With 5G, 6G, and satellite internet driving new filings, H04L is one of the largest active patent classes. Every newly published application in H04L lands in this feed, around 215 a month. Applications publish 18 months after filing, so this feed reveals what MediaTek, Qualcomm, Ericsson, Samsung, Huawei, and dozens of smaller companies were working on in the prior year and a half. Watch this if you compete in networking hardware, advise telecoms on IP strategy, or scout acquisition targets in wireless infrastructure.
What changed
INOVA SEMICONDUCTORS GMBH filed patent application US20260113145A1 on April 23, 2026, disclosing a method for generating bit sequences with limited disparity and run length to enable efficient data transmission on transmission channels. The proposed method achieves deterministic control of physical behavior on transmission channels while reducing resource requirements, minimizing bit errors, and enabling efficient error correction with minimal technical effort. The encoders used are designed with a minimal number of gates and include implicit nesting for particularly advantageous correction of burst errors.
For semiconductor manufacturers and technology companies engaged in data encoding, transmission, or error-correction system design, this patent application represents an innovation in encoding methodology with potential applications in data transmission systems. Parties developing or licensing transmission technologies should monitor the prosecution of this application for potential implications on their intellectual property portfolios.
Archived snapshot
Apr 23, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
EFFICIENTLY TRANSMITTABLE BIT SEQUENCE WITH RESTRICTED DISPARITY, AND ENCODED FORWARD ERROR CORRECTION
Application US20260113145A1 Kind: A1 Apr 23, 2026
Assignee
INOVA SEMICONDUCTORS GMBH
Inventors
Fabian KLUGE, Roland NEUMANN
Abstract
A method is for generating a bit sequence that can be transmitted efficiently and has a limited disparity and a limited run length. The proposed method allows data to be able to be transmitted particularly efficiently on a transmission channel. The physical behavior on a transmission channel can be deterministically controlled despite a reduction in resource requirements. Thus, according to the proposed method, bit errors are minimal and a transmission error can be corrected efficiently, i.e. with minimal technical effort. Furthermore, the encoders used are designed with a minimal number of gates, and the proposed method implicitly includes a form of nesting that allows so-called burst errors to be corrected particularly advantageously.
CPC Classifications
H04L 1/0041 H04L 1/0057
Filing Date
2025-12-18
Application No.
19425573
Parties
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