Digital Injection-Locked Oscillator
Summary
The USPTO published patent application US20260093969A1 for a digital injection-locked oscillator invented by Franck Badets. The invention describes a circuit with an adder adding digital words, a register updating based on clock signals, and a first circuit receiving reference signals at natural frequencies. The application (No. 19341044) was filed September 26, 2025, and published April 2, 2026.
What changed
This patent application describes a digital injection-locked oscillator (2) comprising an adder (100) that adds first and second digital words and outputs a result word over N bits, a register (102) that updates the second word based on the result at each clock period, and a first circuit (200) that receives a reference signal at a natural frequency and calculates a value based on a reference increment. The first circuit outputs the first word by adding this calculated value and a positive control number P. CPC classifications include G06N 3/063, G06N 3/04, and H03K 3/037, indicating applications in neural networks and electronic switching.
Patent applicants and technology companies developing circuits for neural network hardware, timing circuits, or oscillator systems should review this publication to assess potential prior art implications for their own patent applications or R&D activities. No immediate compliance action is required as this is an application publication rather than an issued patent grant.
Archived snapshot
Apr 2, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
DIGITAL INJECTION-LOCKED OSCILLATOR
Application US20260093969A1 Kind: A1 Apr 02, 2026
Inventors
Franck BADETS
Abstract
The present description concerns a digital injection-locked oscillator (2). An adder (100) adds first and second digital words (OP2, OP1) and outputs a third result digital word (RES), the words being over N bits, with N an integer greater than 1. A register (102) updates the second word based on the third word (RES) at each period of a clock signal (clk). A first circuit (200) receives a reference signal (REF) at a natural frequency of an output bit (OUT), and a reference increment, incref. The first circuit calculates a first value (valref) selectively equal to the reference increment incref and to minus the reference increment inc_ref as a function at least of one state of the reference signal. The first circuit outputs the first word at least partly by adding the first value and a positive control number, P, the output bit being a bit of the second word.
CPC Classifications
G06N 3/063 G06N 3/04 H03K 3/037
Filing Date
2025-09-26
Application No.
19341044
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Source
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