Conditional Modular Subtraction Cryptographic Processor Instruction
Summary
The USPTO has published patent application US20260111232A1, filed October 13, 2025, for a conditional modular subtraction cryptographic processor instruction developed by inventors Fabian Boemer, Vinodh Gopal, Gelila Seifu, Sejun Kim, and Jack Crawford. The application describes a processor with circuitry that executes an instruction to subtract second source operand data from first source operand data only when the first operand is greater than or equal to the second operand; otherwise the processor outputs the first operand unchanged. This conditional subtraction operation is classified under cryptographic contexts (CPC H04L 9/008, H04L 9/30) and may relate to cryptographic modulus operations in public-key cryptography implementations.
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USPTO classification H04L covers transmission of digital information: network protocols, modulation schemes, wireless signal processing, coding, encryption in transit, and multiplexing. With 5G, 6G, and satellite internet driving new filings, H04L is one of the largest active patent classes. Every newly published application in H04L lands in this feed, around 215 a month. Applications publish 18 months after filing, so this feed reveals what MediaTek, Qualcomm, Ericsson, Samsung, Huawei, and dozens of smaller companies were working on in the prior year and a half. Watch this if you compete in networking hardware, advise telecoms on IP strategy, or scout acquisition targets in wireless infrastructure.
What changed
The USPTO has published a patent application disclosing a conditional modular subtraction instruction for cryptographic processors. The processor includes first circuitry to decode an instruction indicating first and second source operands, and second circuitry with a processing resource that outputs either the result of the subtraction (when first operand is greater than or equal to second) or the first operand unchanged (when the condition is not met).
Patent applications do not create compliance obligations. Technology companies developing processors, cryptographic libraries, or security-focused computing systems may wish to review the application for prior art awareness or to monitor the prosecution history. The disclosed conditional subtraction mechanism could have implications for efficient implementation of modular arithmetic in public-key cryptographic systems.
Archived snapshot
Apr 25, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
CONDITIONAL MODULAR SUBTRACTION INSTRUCTION
Application US20260111232A1 Kind: A1 Apr 23, 2026
Inventors
Fabian Boemer, Vinodh Gopal, Gelila Seifu, Sejun Kim, Jack Crawford
Abstract
One embodiment provides a processor comprising first circuitry to decode an instruction into a decoded instruction, the instruction to indicate a first source operand and a second source operand and second circuitry including a processing resource to execute the decoded instruction, wherein responsive to the decoded instruction, the processing resource is to output a result of first source operand data minus second source operand data in response to a determination by the processing resource that the first source operand data is greater than or equal to the second source operand data, otherwise the processing resource is to output the first source operand data.
CPC Classifications
G06F 9/30145 G06F 7/49 G06F 7/722 G06F 9/3001 G06F 9/30036 G06F 9/30038 H04L 9/008 H04L 9/30
Filing Date
2025-10-13
Application No.
19357043
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