Analog Neuromorphic Circuits for Dot-Product Operations Implementing Resistive Memories
Summary
The USPTO published patent application US20260093973A1 for analog neuromorphic circuits implementing resistive memories for dot-product operations. Inventors Chris Yakopcic, Tarek M. Taha, and Md Raqibul Hasan disclose a circuit architecture where input voltages representing vector values are processed through paired resistive memories, with resistance values converted to weighted matrix values for neural network computations. The application was filed December 9, 2025, and published April 2, 2026.
What changed
This patent application discloses novel analog neuromorphic circuit architecture using resistive memories to perform dot-product operations for AI and neural network computations. The system applies input voltages representing non-binary vector values to the circuit, where a controller pairs resistive memories and converts paired resistance values into weighted matrix values. Each resulting non-binary value is mapped to the weighted matrix for incorporation into dot-product operations, enabling energy-efficient neuromorphic computing.
Patent publications are informational notices and do not impose compliance requirements on third parties. Technology companies and semiconductor manufacturers developing AI hardware may review this publication to assess potential prior art in neuromorphic circuit design. No action is required, though entities in this space may monitor related USPTO filings for competitive intelligence purposes.
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Apr 2, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
ANALOG NEUROMORPHIC CIRCUITS FOR DOT-PRODUCT OPERATION IMPLEMENTING RESISTIVE MEMORIES
Application US20260093973A1 Kind: A1 Apr 02, 2026
Inventors
Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
Abstract
An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.
CPC Classifications
G06N 3/065 G06F 17/10 G11C 11/54 G11C 13/0021 G11C 13/004
Filing Date
2025-12-09
Application No.
19414041
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