EPO Patent Publication: Adaptive Architecture for Near-Memory Computing

ChangeBridge: EPO Bulletin - AI & Computing (G06N)

Published March 18th, 2026

Detected March 24th, 2026

Summary

The European Patent Office (EPO) has published a new patent application, EP4711982A1, related to an adaptive architecture for near-memory computing. The patent, filed by STMicroelectronics International N.V., details a hardware accelerator designed for efficient data processing.

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What changed

The European Patent Office (EPO) has published patent application EP4711982A1, titled 'ADAPTIVE ARCHITECTURE FOR NEAR-MEMORY COMPUTING SHARING INACTIVE IN-MEMORY COMPUTING DEVICES'. The application, filed by STMicroelectronics International N.V., describes a hardware accelerator featuring functional circuits, a stream switch, data reshape units, and In-Memory Computing (IMC) clusters. A key aspect is the accessibility of inactive IMC devices to serve as dedicated Tightly-Coupled Memory (TCM) for data reshape units, independent of the main stream switch.

This publication represents a new patent filing and does not impose immediate compliance obligations on regulated entities. Companies involved in semiconductor design, hardware acceleration, or AI computing may find the technical details relevant for their research and development strategies. No specific compliance deadlines or penalties are associated with this patent publication.

Source document (simplified)

← EPO Patent Bulletin

ADAPTIVE ARCHITECTURE FOR NEAR-MEMORY COMPUTING SHARING INACTIVE IN-MEMORY COMPUTING DEVICES

Publication EP4711982A1 Kind: A1 Mar 18, 2026

Applicants

STMicroelectronics International N.V.

Inventors

ROSSI, Michele, CAPPETTA, Carmine, MASSA, Riccardo, BOESCH, Thomas, DESOLI, Giuseppe

Abstract

A hardware accelerator includes a plurality of functional circuits, a stream switch, one or more data reshape units coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and one or more In-Memory Computing (IMC) clusters coupled to the stream switch. In operation, inactive IMC devices of at least a subset of the one or more IMC clusters are accessible to at least a subset of the one or more data reshape units, via memory interface independent from the stream switch, to serve as at least part of Tightly-Coupled Memory (TCM) dedicated to at least one of the one or more data reshape units.

IPC Classifications

G06N 3/0464 20230101AFI20260122BHEP G06N 3/063 20230101ALI20260122BHEP

Designated States

AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, ME, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR

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