Memory Circuits and Methods for Encoder/Decoder Dual Mode for Compute-in-Memory
Summary
The USPTO published patent application US20260093968A1 by Taiwan Semiconductor Manufacturing Company (TSMC) covering integrated circuit memory circuits for compute-in-memory (CIM) operations. The patent describes dual-mode encoder/decoder circuits using multiply-accumulate (MAC) operations with data multiplexer paths for efficient processing of neural network and AI workloads.
What changed
TSMC filed patent application US20260093968A1 on December 20, 2024, published April 2, 2026, covering memory circuits and methods for encoder/decoder dual mode operations in compute-in-memory (CIM) architectures. The invention comprises a plurality of CIM circuits with input circuits, memory arrays, data multiplexers with dual data paths, and computing cells configured to perform multiply-accumulate (MAC) operations on stored data elements. CPC classifications include G06N 3/063 (electronic neural networks) and G06N 3/0455 (model architectures). Inventors are Je-Min Hung, Haruki Mori, and Hidehiro Fujiwara.
This patent publication does not impose compliance obligations on any parties. It serves as prior art notice and may affect freedom-to-operate analyses for companies developing AI accelerator chips, neural network processors, or compute-in-memory architectures. Legal and R&D teams should review the claims for potential infringement concerns when designing similar memory-computing integrated circuits.
Archived snapshot
Apr 2, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
MEMORY CIRCUITS AND METHODS FOR ENCODER/DECODER DUAL MODE FOR COMPUTE-IN-MEMORY
Application US20260093968A1 Kind: A1 Apr 02, 2026
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventors
Je-Min Hung, Haruki Mori, Hidehiro Fujiwara
Abstract
An integrated circuit may comprise a plurality of compute-in-memory (CIM) circuits physically formed on a substrate. Each of the plurality of CIM circuits may comprise: an input circuit configured to receive a plurality of first data elements; a memory array coupled to the input circuit and configured to store the plurality of first data elements; a data multiplexer configured to output the plurality of first data elements through a first data path or through a second data path; and a plurality of computing cells coupled to the data multiplexer and configured to perform multiply-accumulate (MAC) operations on the plurality of first data elements and a plurality of second data elements.
CPC Classifications
G06N 3/063 G06N 3/0455
Filing Date
2024-12-20
Application No.
18990207
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