USPTO Patent Grant: Low Power Semiconductor Device
Summary
The USPTO has granted a patent (US12585431B2) to Semiconductor Energy Laboratory Co., Ltd. for a semiconductor device designed for low power consumption and arithmetic operations. The patent details specific circuit and cell configurations utilizing transistors operating in the subthreshold region.
What changed
The United States Patent and Trademark Office (USPTO) has issued patent US12585431B2 to Semiconductor Energy Laboratory Co., Ltd. This patent covers a novel semiconductor device architecture that achieves low power consumption while maintaining arithmetic operation capabilities. Key features include the use of first to third circuits and first and second cells, with transistors operating in the subthreshold region, and specific current flow and potential manipulation mechanisms.
This patent grant is primarily an intellectual property notification. For manufacturers and technology companies involved in semiconductor design and production, this represents a new piece of intellectual property in the field. While it does not impose new regulatory obligations, it may impact product development strategies and licensing considerations for entities operating in this space.
Source document (simplified)
Semiconductor device and electronic device
Grant US12585431B2 Kind: B2 Mar 24, 2026
Assignee
Semiconductor Energy Laboratory Co., Ltd.
Inventors
Yoshiyuki Kurokawa, Munehiro Kozuma, Takeshi Aoki, Takuro Kanemura
Abstract
A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.
CPC Classifications
G06F 7/5443 G06F 17/16 G06G 7/16 G06N 3/065
Filing Date
2020-12-14
Application No.
17785510
Claims
14
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