USPTO Patent Grant: Adaptive DAC Range Optimization

ChangeBridge: Patent Grants - AI & Computing (G06N)

Published March 24th, 2026

Detected March 25th, 2026

Summary

The USPTO has granted a patent (US12587207B2) to International Business Machines Corporation for a system and method to optimize digital-to-analog converter input range values for analog-in-memory computing systems. The patent focuses on improving signal-to-noise ratio by minimizing matrix-vector-multiplication error in the presence of noise.

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What changed

The United States Patent and Trademark Office (USPTO) has issued patent US12587207B2 to International Business Machines Corporation. This patent covers an "Adaptive digital-to-analog converter range optimization" system and method designed to enhance analog-in-memory computing (AIMC) systems. The core innovation involves tuning the input ranges of digital-to-analog converters (DACs) within a tile of processing elements to minimize matrix-vector-multiplication (MVM) error, thereby improving the signal-to-noise ratio in AIMC applications.

This is a grant of intellectual property and does not impose new regulatory obligations on companies. However, it signifies a technological advancement in AI hardware, particularly for in-memory computing. Companies operating in the AI and semiconductor sectors, especially those developing AIMC systems or related components, should be aware of this patented technology. No immediate compliance actions are required, but it may influence future product development and patent licensing strategies.

Source document (simplified)

← USPTO Patent Grants

Adaptive digital-to-analog converter range optimization

Grant US12587207B2 Kind: B2 Mar 24, 2026

Assignee

International Business Machines Corporation

Inventors

Julian Röttger Büchel, Corey Liam Lammie, Athanasios Vasilopoulos, Manuel Le Gallo-Bourdeau, Abu Sebastian

Abstract

System and method for adaptively optimizing digital-to-analog converter input range values for improved signal-to-noise ratio for analog-in-memory computing (AIMC) systems. The method includes a step of tuning the input ranges of the digital-to-analog (DAC) converters of a “tile”, comprised of Processing Elements (PEs) in a crossbar arrangement, to minimize the matrix-vector-multiplication (MVM) error under the presence of some residual noise term that is applied to the output of the MVM. Alternatively, the method includes tuning the input ranges of the DAC converters to minimize the accuracy of a predefined task, e.g., a classification task, under the presence of some residual noise term applied to the output of each matrix-vector-multiplication. The DAC input value range is optimized with respect to a metric that depends on a residual noise source present in AIMC systems. In an embodiment, the system minimizes the error introduced by the residual noise and the quantization.

CPC Classifications

G06N 3/065 G06N 3/08 G06N 3/045 G06N 3/084 G06N 3/048 G06N 3/063 G06N 3/04 G06N 3/0464 G06N 3/09 G06F 7/5443 G06F 17/16 G06F 3/0604 G06F 3/0659 G06F 3/0679 G06F 7/57 G06F 2207/4802 G06F 5/01 G06F 5/012 G06F 7/388 G06F 7/485 G06F 7/4876 G06F 7/575 H03M 1/12 H03M 1/38 H03M 1/66 H03M 1/742 G06G 7/186