The United States Patent and Trademark Office (USPTO) has granted patent US12585925B2 to the Electronics and Telecommunications Research Institute for a novel synaptic circuit. This circuit incorporates a weight memory, a current-mode digital-to-analog converter (C-DAC), a parasitic capacitor correction circuit, and a pre-discharge circuit. The primary innovation is the prevention of charge calculation errors within spike neural networks by correcting parasitic capacitance generated by the C-DAC.

This patent grant is primarily an intellectual property notification and does not impose new regulatory obligations on businesses. However, companies involved in the development or manufacturing of AI hardware, particularly those utilizing neural network architectures or advanced semiconductor designs, may wish to review the patent's claims to understand potential intellectual property landscapes and avoid infringement. The patent is effective March 24, 2026.