This document is a publication of a patent application, US20260086977A1, filed by inventors Honnahuggi Harinath Venkata Naga Ambica Prasad and Eric Norige with the USPTO on November 15, 2024. The application describes a method for generating a Network on Chip (NoC) by computing a virtual channel (VC) mapping that associates each flow with a split VC identifier (including a host VC identifier and a discriminant). It further details generating the NoC with multiply instantiated routers configured with allocated VC identifiers according to the VC mapping, and remapping these identifiers based on inter-router connections and design slices.

As this is a patent application, it does not impose direct regulatory obligations or compliance deadlines on entities. However, it represents a novel technological development in the field of Network-on-Chip architecture. Companies involved in semiconductor design, particularly those developing System-on-Chip (SoC) or Network-on-Chip (NoC) technologies, may find the described methods for virtual channel assignment and compression relevant to their research and development efforts. Compliance officers in this sector should be aware of such technological advancements as they may influence future industry standards or intellectual property landscapes.