Passive Equalizer with Front-End Level-Shifter for Networking Signal Processing
Summary
The USPTO published patent application US20260100869A1 for a passive equalizer with front-end level-shifter (FELS) for networking signal processing. The invention by inventors Shawn Wang, Wenlong Jiang, Arif Amin, and Dai Dai describes a receiver device with a programmable common mode feedback circuit and passive RLC network. The technology enables level shifting of agnostic common-mode signals in AC-coupled or DC-coupled modes for analog signal processing applications.
What changed
The USPTO published patent application US20260100869A1 disclosing a passive equalizer design with front-end level-shifter (FELS) for networking signal processing applications. The invention includes a programmable common mode feedback (CMFB) circuit coupled to a passive RLC network, capable of processing incoming signals in both AC-coupled and DC-coupled modes while performing voltage level shifting using an adjustable current source. The technology is applicable to analog signal processing circuits in networking equipment.
For technology companies and manufacturers involved in networking equipment design, this patent represents potential prior art in the signal processing and equalizer technology space. Parties developing similar passive equalizer or signal processing circuits should review the claims to assess potential overlap with their own intellectual property or product development activities.
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Apr 14, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
Passive Equalizer with Front-End Level-Shifter (Fels)
Application US20260100869A1 Kind: A1 Apr 09, 2026
Inventors
Shawn WANG, Wenlong JIANG, Arif AMIN, Dai DAI
Abstract
Technologies for providing passive equalization with front-end level shifter (FELS) are described. One receiver device includes an input terminal, an analog signal processing circuit; and a front-end equalizer circuit coupled between the input terminal and the analog signal processing circuit. The front-end equalizer circuit includes a programmable common mode feedback (CMFB) circuit and a passive resistor-inductor-capacitor (RLC) network. The programmable CMFB circuit can receive, from the input terminal, an incoming agnostic common-mode (CM) signal having a first voltage level and a differential peak-to-peak voltage in at least one of an alternating current coupled mode (AC-coupled mode) or a direct current-coupled mode (DC-coupled mode). The programmable CMFB circuit can level shift the incoming agnostic CM signal to a CM signal having a second voltage level using an adjustable current source, the second voltage level corresponding to the analog signal processing circuit.
CPC Classifications
H04L 25/03878 H04L 25/03159 H04L 2025/03522
Filing Date
2024-10-03
Application No.
18905987
Named provisions
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