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Neural Network Processor, System-on-Chip, Data Processing Method, and Storage Medium

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Summary

USPTO published patent application US20260093970A1 on April 2, 2026, disclosing a neural network processor and system-on-chip design. Inventors Yongkang XU and Yibo HE filed Application No. 19388033 on November 13, 2025. The invention (CPC: G06N 3/063) relates to systems-on-a-chip technology for neural network operations.

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What changed

The USPTO published patent application US20260093970A1 on April 2, 2026, disclosing a neural network processor and system-on-chip design. The invention relates to systems-on-a-chip technology and includes a first processor core comprising a first buffer for input tensors, a direct memory access controller for data transfer, and an operational array for performing neural network computations. Application No. 19388033 was filed on November 13, 2025, with CPC classification G06N 3/063.

This publication represents a patent application filing and does not impose compliance obligations on regulated entities. Parties developing similar AI hardware or computing technologies should note this as potential prior art and competitive intelligence in the neural network processor space.

Archived snapshot

Apr 2, 2026

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← USPTO Patent Applications

NEURAL NETWORK PROCESSOR, SYSTEM-ON-A-CHIP, DATA PROCESSING METHOD, AND STORAGE MEDIUM

Application US20260093970A1 Kind: A1 Apr 02, 2026

Inventors

Yongkang XU, Yibo HE

Abstract

Disclosed are a neural network processor, a system-on-a-chip, a data processing method, and a storage medium, relating to the technical field of systems-on-a-chip. The neural network processor includes a first processor core, where the processor core includes: a first buffer, configured to buffer a first input tensor corresponding to a first neural network layer in the neural network model; a first direct memory access controller, configured to read a second input tensor corresponding to the first neural network layer from a second buffer, and write the second input tensor into an operational array; and the operational array, configured to read the first input tensor from the first buffer, and perform a first operation based on the first input tensor and the second input tensor, to obtain a first output tensor.

CPC Classifications

G06N 3/063

Filing Date

2025-11-13

Application No.

19388033

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Last updated

Classification

Agency
USPTO
Published
April 2nd, 2026
Instrument
Notice
Legal weight
Non-binding
Stage
Draft
Change scope
Minor
Document ID
US20260093970A1

Who this affects

Applies to
Technology companies
Industry sector
3341 Computer & Electronics Manufacturing
Activity scope
Patent Filing
Geographic scope
United States US

Taxonomy

Primary area
Intellectual Property
Operational domain
Legal

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