Maximum Likelihood Sequence Detection Circuit, Detection Method, Detection Apparatus and Electronic Device
Summary
The USPTO published patent application US20260100868A1 on April 9, 2026, filed by inventors Jinxin LI and Xiaofan LU. The application covers a maximum likelihood sequence detection circuit with an equalization processing module, state selection module, and detection module for communications systems. CPC classifications include H04L 25/03318 and H04L 25/03057. The application was filed on June 27, 2023, under Application No. 19113953.
What changed
The USPTO published patent application US20260100868A1 covering a maximum likelihood sequence detection circuit for communications. The circuit includes an equalization processing module for processing ADC output signals, a state selection module that determines target signal states based on soft values, and a detection module for performing maximum likelihood sequence detection and outputting decoded detection results.
This document is a patent application publication, not a granted patent, and does not create any compliance obligations. It serves as public notice of the claimed invention. Affected parties may monitor the application status for examination updates or potential prior art considerations.
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Apr 14, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
MAXIMUM LIKELIHOOD SEQUENCE DETECTION CIRCUIT, DETECTION METHOD, DETECTION APPARATUS AND ELECTRONIC DEVICE
Application US20260100868A1 Kind: A1 Apr 09, 2026
Inventors
Jinxin LI, Xiaofan LU
Abstract
Provided in the present disclosure are a detection circuit, a detection method and a detection apparatus for a maximum likelihood sequence, and an electronic device. The detection circuit for detecting a maximum likelihood sequence includes an equalization processing module, configured to perform equalization processing on an output signal from an analog-to-digital converter (ADC) and output a soft value based on the output signal from the ADC; a state selection module, connected to the equalization processing module and configured to determine a target signal state based on the soft value; and a detection module, connected to the state selection module and configured to perform maximum likelihood sequence detection based on the target signal state and output a detection result after decoding.
CPC Classifications
H04L 25/03318 H04L 25/03057
Filing Date
2023-06-27
Application No.
19113953
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