Differential Loop PUF Circuit for Cryptographic Key Generation
Summary
The USPTO published patent application US20260100828A1 for a Differential Loop Physically Unclonable Function (PUF) circuit designed for cryptographic key generation. The invention by Sylvain Guilley and Florent Lozac'h includes two parallel loops with delay elements forming free-running oscillators, where applied challenges to each loop generate oscillation counts compared by a subtractor to produce cryptographic keys based on reliability conditions.
What changed
The USPTO published patent application US20260100828A1 disclosing a Differential Loop Physically Unclonable Function (PUF) circuit for cryptographic key generation. The system uses two identical parallel loops with delay elements forming free-running oscillators, where enrolled challenges are applied to each loop and a subtractor determines oscillation differences to generate secret key bits subject to reliability conditions.
Affected parties including semiconductor manufacturers, security device makers, and technology companies developing cryptographic systems should monitor this application for potential infringement concerns and freedom-to-operate analysis. The PUF circuit technology has applications in secure key generation for IoT devices, hardware security modules, and embedded systems requiring unclonable identifier generation.
What to do next
- Monitor for patent grant status
- Review claims for infringement analysis
Archived snapshot
Apr 11, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
DIFFERENTIAL LOOP PHYSICALLY UNCLONABLE FUNCTION
Application US20260100828A1 Kind: A1 Apr 09, 2026
Inventors
Sylvain GUILLEY, Florent LOZAC'H
Abstract
A system includes a Physically Unclonable Function (PUF) circuit including two identical loops, in parallel, having first and second loops, each having delay elements in series, forming a Free-Running Oscillator to oscillate between two states. A first challenge is applied to the first loop and a second challenge is applied to the second loop. A subtractor receives as inputs the number of oscillations in the first loop and the number of oscillations in the second loop, for each applied challenge, and determines a difference value between the received numbers of oscillations. The system generates a secret key, including bits, in response to application of enrolled challenges to the PUF circuit, each bit corresponding to an applied enrolled challenge and corresponding to the sign of the difference value provided by the subtractor in response to the applied enrolled challenge, if the difference meets a reliability condition.
CPC Classifications
H04L 9/0866 G06F 21/75 H04L 9/3278
Filing Date
2025-10-06
Application No.
19351170
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