Design Rule Enforcement System for Semiconductor Devices
Summary
USPTO published patent application US20260111638A1 on April 23, 2026, filed by inventors Fangyi Chang and Hung-Chih Ou on October 22, 2024. The application covers a neural network-based system for semiconductor design rule enforcement, combining a feature extractor module with a design rule checker and layout diagram modifier. The system uses a first neural network for DRC compliance checking and a second neural network for layout modification to reduce violations.
About this source
USPTO classification G06N covers computer systems based on specific computational models: neural networks, knowledge representation, fuzzy logic, expert systems, evolutionary algorithms. With the AI patent boom, this is one of the most-filed application classes in the office. Every newly published application in G06N lands in this feed, around 230 a month. Patent applications publish 18 months after filing, so this feed reveals what AI labs and companies were working on in the prior year and a half. Watch this if you compete in machine learning, file freedom-to-operate analyses, scout acquisition targets in AI infrastructure, or track which research groups are converting publications to patents. GovPing pulls each application with the filing number, title, applicant, and abstract.
What changed
USPTO published patent application US20260111638A1 for a system and method of design rule enforcement in semiconductor device manufacturing. The application discloses a system comprising a feature extractor module and a design rule enforcement module with two components: a design rule checker (DRC) module based on a first neural network, and a layout diagram modifier (LDM) module based on a second neural network. The DRC module checks subject layout features against design rules and identifies violations, while the LDM module modifies DR-violating features to produce a validated layout diagram. For semiconductor manufacturers and EDA software developers, this patent application indicates continued industry investment in AI-driven design verification tools, potentially influencing future design-for-manufacturability workflows and competitive positioning in the semiconductor design automation market.
Archived snapshot
Apr 24, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
SYSTEM FOR DESIGN RULE ENFORCEMENT, METHOD OF OPERATING SAME AND METHOD OF MANUFACTURING SAME
Application US20260111638A1 Kind: A1 Apr 23, 2026
Inventors
Fangyi CHANG, Hung-Chih OU
Abstract
A system (for manufacturing a semiconductor device) includes an unvalidated subject layout diagram representing the semiconductor device, the system being configured to generate the following including: a feature extractor module configured to extract subject features that at least partially comprise the unvalidated subject layout diagram; and a design rule (DR) enforcement module including a DR checker (DRC) module and layout diagram modifier (LDM) module, the DRC module being configured to check the subject features for compliance with corresponding design rules in a set thereof and to identify which of the design rules are being violated and corresponding DR-violating subject features, and the LDM module being configured to attempt reducing the DR violations by modifying the DR-violating subject features resulting in a validated subject layout diagram; the DRC module being based on a first neural network; and the LDM module being based on a second neural network.
CPC Classifications
G06F 30/3323 G06N 3/045 G06N 3/0464 G06N 3/0475 G06N 3/092
Filing Date
2024-10-22
Application No.
18922943
Parties
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