Deep Neural Network Multi-Terminal Logic Gates Patent
Summary
USPTO published patent application US20260099702A1 for a deep neural network circuit with multiple layers formed of multi-terminal logic gates. Inventor Fabio Lorenzo Traversa filed the application on December 11, 2025, under application number 19416277. The circuit includes logic gates arranged into layers with logical connectors between adjacent layers, where each connector has one of multiple states and can be trained to implement functions.
What changed
USPTO published a patent application for a deep neural network circuit architecture using multi-terminal logic gates. The invention describes logic gates arranged in multiple layers with logical connectors between adjacent layers, where each connector has one of multiple states and the circuit can be trained by adjusting connector states to implement functions.
For companies developing neural network hardware or AI circuit architectures, this patent publication signals existing IP claims in this technical space and may influence R&D directions or design decisions around multi-terminal logic gate implementations.
Archived snapshot
Apr 18, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
DEEP NEURAL NETWORK WITH MULTIPLE LAYERS FORMED OF MULTI-TERMINAL LOGIC GATES
Application US20260099702A1 Kind: A1 Apr 09, 2026
Inventors
Fabio Lorenzo Traversa
Abstract
A deep neural network circuit with multiple layers formed of multi-terminal logic gates is provided. In one aspect, the neural network circuit includes a plurality of logic gates arranged into a plurality of layers and a plurality of logical connectors arranged between each pair of adjacent layers. Each of the logical connectors connects the output of a first logic gate to the input of a second logic gate and each of the logical connectors has one of a plurality of different logical connector states. The neural network circuit is configured to be trained to implement a function by finding a set of the logical connector states for the logical connectors such that the neural network circuit implements the function.
CPC Classifications
G06N 3/063
Filing Date
2025-12-11
Application No.
19416277
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