Decoder Circuit FSK Signals Sampling Point Drift Correction
Summary
USPTO published patent application US20260100871A1, filed September 5, 2025, for a decoder circuit correcting sampling point drift in FSK modulated signals. The invention by inventors Carlo Porcaro and Daniele Colonna includes sampling point drift correction circuitry that varies sample counter end-of-count values when accumulated error reaches a drift reference threshold. Application number 19319951 has CPC classification H04L 27/14.
What changed
USPTO published patent application US20260100871A1 disclosing a decoder circuit for FSK (Frequency Shift Keying) modulated signals with sampling point drift correction. The decoder receives demodulated symbol sequences and uses sampling point drift correction circuitry to vary sample counter end-of-count values when accumulated sampling point error reaches a drift reference threshold. Logic circuitry detects level transitions to assert error-in-transmission or end-of-transmission signals.
Patent applicants and manufacturers of telecommunications decoder equipment should monitor this application to understand emerging sampling point correction techniques in signal processing. The published application provides technical disclosure of FSK signal handling methods relevant to receiver and transmission system design.
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Apr 14, 2026GovPing captured this document from the original source. If the source has since changed or been removed, this is the text as it existed at that time.
DECODER CIRCUIT, CORRESPONDING RECEIVER AND TRANSMISSION SYSTEM
Application US20260100871A1 Kind: A1 Apr 09, 2026
Inventors
Carlo Porcaro, Daniele Colonna
Abstract
A decoder receives, from a demodulator of FSK modulated signals, a sequence of demodulated symbols having level transitions between adjacent demodulated symbols and at least a part of the demodulated symbols having level transitions between adjacent signaling elements therein. A sample counter samples the sequence of demodulated symbols. A comparator performs comparison of the samples with at least one reference threshold and the results for at least three adjacent signaling elements in the decoded symbols are stored in a buffer. Logic circuitry asserts an error-in-transmission signal or an end-of-transmission signal in response to an isolated or persisting absence of level transitions detected over a reference period of time. Sampling point drift correction circuitry coupled to the buffer circuit varies the end-of-count value of the sample counter in response to an accumulated sampling point error reaching a drift reference threshold.
CPC Classifications
H04L 27/14
Filing Date
2025-09-05
Application No.
19319951
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