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USPTO Patent Granted for Power Supply Protection Circuit

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Published March 24th, 2026
Detected March 25th, 2026
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Summary

The USPTO has granted a patent (US12587011B2) to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC for a substrate parasite reduction technique in power supply protection circuits. This invention aims to prevent malfunctions in high power integrated circuits used in automotive or industrial applications.

What changed

The United States Patent and Trademark Office (USPTO) has granted patent US12587011B2 for a "Substrate parasite reduction technique" to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC. The patent covers a protection circuit designed for automotive or industrial high power integrated circuits, specifically addressing reverse battery and reverse current protection. The disclosed circuit aims to prevent the formation of parasitic devices that could lead to malfunction or failure to power on in the integrated circuits.

This patent grant is primarily an intellectual property development and does not impose new regulatory obligations on regulated entities. However, companies involved in the design or manufacturing of automotive or industrial high power integrated circuits, particularly those utilizing MOSFETs for power supply protection, may consider this patent in their product development and intellectual property strategies. The patent was filed on September 6, 2023, and granted on March 24, 2026.

Source document (simplified)

← USPTO Patent Grants

Substrate parasite reduction technique

Grant US12587011B2 Kind: B2 Mar 24, 2026

Assignee

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventors

Srinivasa Prasad Soundararajan

Abstract

A protection circuit is disclosed for use in automotive or industrial high power integrated circuits equipped with reverse battery protection and reverse current protection. The protection circuit prevents formation of parasitic devices that could cause the high power integrated circuit to malfunction or fail to turn on. The protection circuit features asynchronous operation of a pair of MOSFETs coupled between a power supply and a load. The protection circuit can be engaged at start-up or in response to transient conditions associated with a fault.

CPC Classifications

H02H 3/18 H02H 7/18 H02H 11/002 H02H 3/05 H02J 7/0034

Filing Date

2023-09-06

Application No.

18461781

Claims

20

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Named provisions

Substrate parasite reduction technique

Source

Analysis generated by AI. Source diff and links are from the original.

Classification

Agency
USPTO
Published
March 24th, 2026
Instrument
Notice
Legal weight
Non-binding
Stage
Final
Change scope
Minor
Document ID
US12587011B2

Who this affects

Applies to
Manufacturers
Industry sector
3341 Computer & Electronics Manufacturing 3364 Aerospace & Defense
Activity scope
Product Development Intellectual Property Management
Geographic scope
United States US

Taxonomy

Primary area
Intellectual Property
Operational domain
R&D
Topics
Automotive Semiconductors

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