USPTO Patent Granted for Boost Circuit and Power Supply
Summary
The USPTO has granted a new patent (US12587098B2) for a synchronous coupled boost circuit, a boost circuit, and a power supply apparatus. The patent was assigned to THINKING POWER TECHNOLOGY (SHENZHEN) LIMITED and lists Zhenyuan Wu as the inventor. The patent details specific circuit configurations for improved power supply efficiency.
What changed
The United States Patent and Trademark Office (USPTO) has granted patent US12587098B2 for a synchronous coupled boost circuit, a boost circuit, and a power supply apparatus. The patent, assigned to THINKING POWER TECHNOLOGY (SHENZHEN) LIMITED, details specific transistor and winding connections within the circuit to achieve its functionality. This grant represents the formal recognition of a novel invention in the field of power electronics.
This patent grant does not impose new regulatory obligations on businesses. It is a grant of intellectual property rights to the assignee. Companies involved in the design or manufacturing of power supplies may wish to review the patent to ensure their products do not infringe on the granted claims, though this is typically a matter for legal counsel and not immediate compliance action.
Source document (simplified)
Synchronous coupled boost circuit, boost circuit and power supply apparatus
Grant US12587098B2 Kind: B2 Mar 24, 2026
Assignee
THINKING POWER TECHNOLOGY (SHENZHEN) LIMITED
Inventors
Zhenyuan Wu
Abstract
Disclosed are a synchronous coupled boost circuit, a boost circuit, and a power supply apparatus. In the synchronous coupled boost circuit, the source of the first upper transistor is connected to the non-dotted terminal of the first winding of the coupled inductor and the drain of the first lower transistor, the drain of the first upper transistor is connected to the power output terminal; the source of the second upper transistor is connected to the non-dotted terminal of the second winding of the coupled inductor and the drain of the second lower transistor, the drain of the second upper transistor is connected to the power output terminal; the source of the first lower transistor is grounded; and the source of the second lower transistor is grounded.
CPC Classifications
H02M 3/1582 H02M 3/156 H02M 3/157 H02M 3/158 H02M 3/1584 H02M 3/1586 H02M 3/285 H02M 3/33561 H02M 7/49 H02M 1/045 H02M 7/006 H02M 7/06 H02M 7/068 H02M 7/153 H02M 7/10 H02M 1/083 H02M 7/103 H02M 7/106 H02M 7/19 H02M 7/08 H02M 7/17 H02M 2001/007 H02M 7/493 H02M 7/53806 H02M 7/5381 H02M 7/483 H02M 7/217 H02M 7/538466 H02M 7/5387 H02M 7/53871 H02M 7/53873 H02M 7/53875 H02M 1/084 H02M 1/0845 H02M 1/007 H02M 1/0009 H02M 1/0095 H02M 1/08 H02M 1/088 H02M 3/1588 H02M 7/5395 H02M 1/14 H02M 1/0043 H02M 1/0074 H02M 1/0077 H02M 1/0045 H02M 1/0006 H02J 3/46 H02J 3/38
Filing Date
2024-01-31
Application No.
18428279
Claims
19
Named provisions
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