Operation circuit and chip

Abstract

An operation circuit and a chip pertaining to the field of integrated circuit design technology are disclosed by the present application. The circuit includes a capacitor charging/discharging module and an error amplification module electrically connected to the capacitor charging/discharging module. The capacitor charging/discharging module is configured to receive a first signal and a third signal that are external to the capacitor charging/discharging module and to output a feedback signal. The error amplification module is configured to receive the feedback signal and a second signal that is external to error amplification module and to output, based on the received feedback and second signals, a target signal to the capacitor charging/discharging module. In a steady state, values of the target, first, second and third signals satisfy a predefined mathematical relationship.

CPC Classifications