Decision-feedback equalizer slicers for pulse amplitude modulation signaling

Abstract

An interface circuit includes a current summer, a pair of slicers and a pair of replica summing circuits. The current summer is configured to sum currents representative of a signaling state of an input signal in a sequence of transmission intervals. A first slicer is configured to generate a first decision based on a comparison of an output of the current summer and voltage level of a first threshold signal. A second slicer is configured to generate a second decision based on a comparison of the output of the current summer and voltage level of a second threshold signal. A first replica summing circuit is configured to generate the first threshold signal based on a common-mode signal that is representative of the common-mode voltage at the input of the current summer. A second replica summing circuit is configured to generate the second threshold signal based on the common mode signal.

CPC Classifications