Method and apparatus of deskew process for a circuitry, computer storage medium, and terminals

Abstract

A circuitry, method, computer storage medium, and terminal for deskew processing include: receiving data lanes, clock signal lanes, deskew control modules, and deskew modules. The receiving data lane receives input data signals, which are in alternating standard sequence. The clock signal lane receives input clock signals. The deskew control module is connected to the receiving data lane and is set to acquire the sample data obtained by sampling the data signal of the data signal lane by the clock signal of the clock signal lane with a preset duration, and determine the delay information based on the sample data. The deskew module is connected to the deskew control module and is set to adjust the phase offset of both the clock signal and the data signal based on the delay information. The embodiments of the present invention sample the data signal and determine the delay information by the deskew control module, adjust the phase offset by the delay information, simplifying the circuitry composition of phase calibration.

CPC Classifications