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Systems and methods of tiled concatenation of forward error correction codes

Grant US12580591B1 Kind: B1 Mar 17, 2026

Assignee

Cisco Technology, Inc.

Inventors

Murat Azizoglu

Abstract

In part, in one aspect, the disclosure relates to a tiled concatenation system. The system may include an encoder system comprising one or more outer encoders, wherein at least one outer encoder is configured to generate n bits from k bits; a framer comprising an input, wherein the input receives T groups of n bits, wherein the framer is configured to rearrange the T groups of n bits to generate a set of T tiles, wherein each tile comprises L*C bits to generate a frame comprising L rows of K bits, the framer configured to rearrange a fraction of C bits per tile per row of each frame such that the fraction of high quality and low quality bits at the encoder output will be balanced among the tiles using an inner encoder; and the inner encoder comprising the fraction of C bits.

CPC Classifications

H03M 13/253 H03M 13/255 H03M 13/2703 H03M 13/1102 H04L 1/0041 H04L 1/0057 H04L 1/0071

Filing Date

2024-03-15

Application No.

18606310

Claims

20