Control of debug port access to data in a memory device, operating method of the same, and memory system

Abstract

A memory device includes one or more non-volatile memories configured to store user data and at least one key related to the user data; a network-on-chip comprising a bus manager configured to manage access to the user data and the at least one key; and a debug port directly connected to a host and configured to receive a request from the host, wherein the bus manager is further configured to, based on the debug port being activated, determine whether to allow access of the host to the user data and the at least one key based on classification information.

CPC Classifications