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SYSTEM-LEVEL TECHNIQUES FOR ERROR CORRECTION IN CHIP-TO-CHIP INTERFACES

Application US20260088927A1 Kind: A1 Mar 26, 2026

Inventors

Millind MITTAL, Krishnan SRINIVASAN, Kenneth MA

Abstract

Some examples described herein provide for interconnect in chiplet systems, for example system-level techniques for error correction in chip-to-chip interfaces. In an example, a method of error correction includes receiving, at a first chiplet, a data message via a set of interconnect, and transmitting a first control message that requests retransmission of the data message based on detecting an error associated with receiving the data message. The method also includes transmitting one or more instances of a second control message that indicates an idle operation at the first chiplet until the first chiplet receives a third control message that triggers an end of a retransmission mode. The method also includes transmitting a fourth control message frame indicating the end of the retransmission mode, and receiving a retransmission of the data message from the second chiplet.

CPC Classifications

H04L 1/0041 H04L 1/0025 H04L 49/9005

Filing Date

2025-12-02

Application No.

19406932