DEMODULATOR CIRCUIT

Abstract

A demodulator includes a sampling stage, a hold stage, and an output stage. The sampling stage includes at least one mixer configured to be controlled by complementary clock signals synchronous with a carrier frequency of an input signal to demodulate the input signal and generate a sampled signal. The hold stage includes at least a first capacitor circuit configured to output the sampled signal after delaying the sampled signal as a first hold signal and a second capacitor circuit configured to output the sampled signal after delaying the sampled signal as a second hold signal. The output stage is configured to alternately couple the first hold signal and the second hold signal as a demodulated output signal.

CPC Classifications