DISCRETE-TIME LINEAR EQUALIZER FOR DISCRETE-TIME ANALOG FRONT-END

Abstract

An apparatus comprises a discrete-time linear equalizer circuit. The discrete-time linear equalizer circuit includes a sample and hold circuitry including multiple switched-capacitor circuits. The multiple switched-capacitor circuits include at least a switched-capacitor circuit of a pre-cursor tap, a switched-capacitor circuit of a cursor tap, and a switched-capacitor circuit of a post-cursor tap. A clock-driven switch circuitry is to switchably couple a capacitor of the switched-capacitor circuit of the pre-cursor tap to a negative signal input over a first time period, a capacitor of the switched-capacitor circuit of the cursor tap to a positive signal input over a second time period, and a capacitor of the switched-capacitor circuit of the post-cursor tap to the negative signal input over a third time period. The clock-driven switch circuitry is to switchably couple the capacitors of the switched-capacitor circuits in parallel over a fourth time period.

CPC Classifications