SIGNALING THAT INCLUDES INVERSION INFORMATION AND LINK PARITY INFORMATION

Abstract

In some implementations, a system may invert, based on an inversion configuration, one or more portions of first data to generate second data. The system may generate link parity information associated with the second data and the inversion configuration. The system may communicate, from a host system to a memory apparatus and via a first bus of a host interface, a message comprising the second data, the inversion configuration, and the link parity information from the host system to the memory apparatus. The system may store the second data to one or more memory arrays of the memory apparatus.

CPC Classifications