TECHNOLOGIES FOR QUALITY OF SERVICE BASED THROTTLING IN FABRIC ARCHITECTURES

Abstract

Disclosed in the present disclosure is an apparatus comprising a first multi-chip package. The first multi-chip package comprises: a first plurality of cores, a first interconnect coupled to the first plurality of cores, an interconnect link to transmit data, a second interconnect coupled to the first interconnect via the interconnect link, a first memory interconnect to couple the first plurality of cores to a first system memory device, the first plurality of cores to access the first memory interconnect via the first interconnect, the interconnect link, and the second interconnect. The first memory interconnect and first system memory device are to be associated with a first non-uniform memory access (NUMA) domain. A first multi-chip package is coupled to a second multi-chip package associated with a second NUMA domain. A first NUMA domain identifier is to be associated with the first NUMA domain and a second NUMA domain identifier is to be associated with the second NUMA domain. The first multi-chip package further comprises: monitoring circuitry for monitoring utilization of a resource associated with the first NUMA domain, the monitoring circuitry including one or more model-specific registers, MSRs, to store counter values associated with requests to access the resource, and enforcement circuitry for limiting utilization of the resource from within the first NUMA domain or from the second NUMA domain in accordance with one or more of the counter values. The counter values include a first counter value associated with utilization of the resource from within the first NUMA domain and a second counter value associated with utilization of the resource from at least the second NUMA domain.

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